A typical phase-locked loop (PLL) system includes a phase comparator, a charge pump, a low-pass filter and a voltage-controlled oscillator (VCO). These elements are coupled together to form a closed-loop system wherein the phase comparator measures differences in phase between an input reference signal and a feedback signal from the output of the VCO. Any detected difference generates an error signal which is fed through the charge pump to the filter for supply to the VCO. The charge pump, positioned between the phase comparator and the filter, provides either a positive current source to add charge to the filter or a negative current source to remove charge from the filter based upon the error signal output from the phase comparator. The VCO utilizes the control voltage across the filter to minimize the frequency difference between the PLL feedback signal and the input reference signal.
One embodiment of a PLL charge pump circuit having positive and negative current sources is presented in U.S. Pat. No. 4,814,726. This patent describes a phase detector and charge pump circuit combination for use in a digital PLL circuit. The phase detector includes a reset circuit that responds to the charge pump when the charge pump is simultaneously sourcing and sinking current. The charge pump's up and down circuits are balanced in an attempt to minimize conduction during a phase-locked condition. However, there is no attempt to compensate for second order current mismatching resulting from the presence of a control voltage on the output node of the charge pump.
Existing PLL charge pump circuits often output a current that is a function of the control voltage across the filter. Such circuits typically exhibit an offset error when the PLL system is in phase-locked condition. This is because the current sources have a finite output impedance due to channel length modulation (CMOS technology) or base width modulation (bipolar technology), meaning that the output currents are a weak but significant function of output voltage. This relationship can result in an amplitude mismatch between the output of the positive current source and the output of the negative current source when in phase-locked condition. Such current mismatching is exhibited as a static offset error within the PLL system and manifested as a phase difference between the input reference clock and the PLL output clock. Because PLL systems are widely used in clock distribution applications, avoidance of a phase difference between the reference system clock and the PLL output clock is desirable since any phase difference degrades system performance. A charge pump circuit in accordance with the present invention addresses this concern.